1. Field of the Invention
The present invention relates to an inspection substrate to be used for detecting a wiring defect, a failure spot and the like in an array substrate of a display device.
2. Description of the Related Art
In recent years, commercialization of a high-function liquid crystal display device capable of high-definition display though being high-density and large-capacity has progressed. Among such liquid crystal display devices, one of an active matrix type has been frequently used. The active matrix type liquid crystal display device includes an array substrate, in which each of regions individually partitioned by plural scan lines and plural signal lines which intersect each other is defined as a pixel, and a switching element, a pixel electrode and the like are arranged for each pixel. In the active matrix type liquid crystal display device, a crosstalk between adjacent pixels is small, high-contrast display is obtained, transmission display is enabled, and area enlargement thereof is also easy.
In the active matrix type liquid crystal display device, as definition thereof has been increased, microprocessing for wiring lines and contact holes has become necessary, and it has been required to keep a high process level. Therefore, in recent years, a process level chip (hereinafter, referred to as a “PL chip”) in which only the wiring lines in the array substrate are provided has been manufactured, and a state of the wiring lines in the PL chip has been electrically measured by means of a tester, or optically evaluated by means of a defect inspection apparatus. Moreover, also for the actual array substrate, an electrical defect thereof is inspected by use of an array tester, a failure thereof is analyzed, and a management and improvement of the process level are achieved.
However, according to the above-described method, there are problems that the defect detected in the PL chip does not always coincide with the defect in the array substrate, and that one regarded as the defect in the array substrate is not detected in the PL chip.
Moreover, according to the above-described method, the defect detectable in the PL chip is limited only to defects in which abnormalities are observed on a planer wiring pattern and an exterior appearance. Therefore, there is a problem that an evaluation for the array substrate must be concurrently used for characteristics as a device, which include characteristics of the switching elements and the contact holes.
Furthermore, also in the case of inspecting the array substrate by means of the array tester, a defect detection capability thereof is insufficient, and a position where the defect occurs cannot be specified in some cases depending on a type of the defect. Therefore, there is a problem that the management and improvement of the process level cannot be performed sufficiently.
This point is described with reference to FIG. 1 and FIG. 2. FIG. 1 is a plan view showing an example of a wiring pattern in the PL chip. FIG. 2 is a plan view showing a wiring pattern with a contact chain structure.
In FIG. 1, a meandering wiring line 181 is formed of a metal film, and to both ends of the meandering wiring line 181, electrode pads 183a and 183b are individually connected. In order to detect a break of the meandering wiring line 181, a voltage is applied between both of the electrode pads 183a and 183b, and it is monitored whether or not a current flows therethrough. When the current does not flow, the break occurs in the meandering wiring line 181.
In FIG. 2, a meandering wiring line 191 is formed with the contact chain structure, in which plural ones formed by alternately arranging first metals 193 and second metals 195 and electrically connecting ends of the respective metals to one another by contact holes 197 are arranged. To both ends of the contact chain structure, electrode pads 199a and 199b are connected. In order to detect a break of the meandering wiring 191, a voltage is applied between both of the electrode pads 199a and 199b, and it is monitored whether or not a current flows therethrough. When the current does not flow, the break occurs in the meandering wiring 191.
However, in both of the cases, for example, when abnormalities are not observed on exterior appearances of the wiring lines, a position where the break occurs cannot be specified.
Moreover, in recent years, used has been a method for managing an occurrence rate of the defect and a state of the malfunction in a manufacturing line in such a manner that a process level chip in which only various lines and spaces (L/S) are arranged for the inspection is fabricated in the manufacturing line, and that the process level chip is electrically measured by means of the tester or optically evaluated by means of the defect inspection apparatus.
In the electrical defect inspection using the array tester, an actual array substrate is used as the inspection substrate, and the respective inspection pins of the array tester are connected to the respective signal lines on the array substrate, thus performing the measurement. In the measurement, the switching elements of the respective pixels on the array substrate are switched on, and thereafter, charges are stored in the storage capacitors of the respective pixels through the respective signal lines, and the amount of stored charges is measured through the inspection pins of the array tester. By performing defect analysis for an obtained measurement result, a leakage defect of the amount of charges stored in the storage capacitors of the respective pixels, characteristic abnormalities of the switching elements, short circuit/break defect of the wiring lines, and the like are detected. Based on a result of the detection, the process level of the manufacturing line is managed and improved.
However, in the detection result by means of the array tester, the smaller the storage capacitor to be inspected is, the larger an influence of noise owing to parasitic capacitance becomes in terms of the configuration of the array tester concerned. In general, the influence from the parasitic capacitance becomes larger as the storage capacitor is moved away from a feeding end of each signal line, and accordingly, an output result is outputted in a state where a gradation is applied thereto in the direction of the signal lines. Moreover, approximately 200 signal lines are processed simultaneously in usual, and there is a problem that the output result is outputted as streak unevenness between the signal lines owing to variations in sensitivity for the input signals of the respective inspection pins of the array tester.
Moreover, there is a problem that the process level chip cannot be accurately evaluated because, owing to the influence from the parasitic capacitance of each signal line and the variations in sensitivity for the input signals of the respective inspection pins of the array tester, an abnormal pixel is not sometimes detected even if there are abnormalities in the characteristics of the switching elements of the pixels.
Meanwhile, in the inspection of the defect by means of the array tester, only the electrical characteristics of the respective pixels can be measured. Accordingly, in order to specify a kind of the defect such as to whether the detected defect is a short-circuit defect or a break defect, it is necessary to use a pattern inspection by means of an optical appearance inspection apparatus in combination.